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| rev. 4134c?8051?09/04 1 features ? 80c51 compatible cpu core high-speed architecture ? x2 speed improvement capability (6 clocks/machine cycle) ? 16 mhz in standard or x2 mode ? 256 bytes ram ? 256 bytes xram ? 12k bytes rom/otp program memory ? two 16-bit timer/counters t0, t1 ? 5 channels programmable counter array with high-speed output, compare/capture, pulse width modulation and watchdog timer capabilities ? spi interface (master and slave mode) ? interrupt structure with: ? 6 interrupt sources ? 4 interrupt priority levels ? power supply: 3 - 5.5v ? temperature range: industrial (-40 o c to 85 o c), automotive (-40 o c to 125 o c) ? package: ssop16, ssop24 description the at8xc5103 is a high-performance rom /otp version of the 80c51 8-bit micro- controller in 16 and 24-pin packages. the at8xc5103 contains a standard c51 cpu core with 12 kbytes rom/otp pro- gram memory, 256 bytes of internal ram, 256 bytes of extended internal ram, a 5- sources 4-level interr upt system, two timer/co unters and a spi serial bus controller. the at8xc5103 is also dedicated for analog in terfacing applications . for this, it has a five channels programmable counter array. in addition, the at8xc5103 implements the x2 speed improvement mechanism. the x2 feature allows to keep the same cp u power at a divided by two oscillator frequency. the fully static design of the at8xc5103 a llows to reduce system power consumption by bringing the clock frequency down to any value, even dc, without loss of data. low-pin count 8-bit microcontroller at87c5103 at83c5103
2 at8xc5103 4134c?8051?09/04 block diagram notes: 1. alternate function of port 1. 2. alternate function of port 3. timer 0 int ram 256x8 t0 xtal2 xtal1 cpu timer 1 ctrl int0 c51 core (3) (3) port 1 p1 p3 ib-bus vss vcc rom 12 k *8 cex0-4 xtal osc (1) port 3 pca miso (1) mosi (1) spsck (3) spi ss (1) rst eci (1) 256x8 parallel i/o ports exram p4 port 4 int1 (3) t1 (3) 3 at8xc5103 4134c?8051?09/04 pin configurations xtal1 vcc vss 1 rst /vpp xtal2 p1.2/eci/dig2 p3.2/dig0/int0 p3.6/spick p3.4/dig1/t0 p1.7/cex4/ss p1.6/cex3 p1.5/cex2 p1.4/cex1 p1.3/cex0 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 p1.1/mosi p1.0/miso ssop16 p1.1/mosi p1.0/miso vcc xtal2 p1.5/cex2 vss xtal1 p1.2/eci/dig2 rst /vpp p3.1 p3.6/spick 1 2 3 4 5 6 7 8 16 15 14 13 9 10 11 12 p1.6/cex3 p3.7 p3.5/t1 20 19 18 17 24 23 22 21 p3.4/dig1/t0 p4.0 p4.1 p4.2 p1.3/cex0 p1.4/cex1 p3.0 p1.7/cex4/ss p3.3/int1 p3.2/dig0/int0 ssop24 4 at8xc5103 4134c?8051?09/04 pin description mnemonic type name and function v ss i ground: 0v reference v cc i power supply: 3.0v or 5.5v p1.0 - p1.7 i/o port 1: port 1 is an 8-bit programmable i/o port with internal pull-up alternate functions for port 1 include: i/o miso (p1.0): master in, slave out of the spi controller i/o mosi (p1.1): master out, slave in of the spi controller i/o dig2 (p1.2): programmable as output with push-pull eci: external clock for pca i/o cex0 (p1.3): capture/compare external i/o for pca module 0 i/o cex1 (p1.4): capture/compare external i/o for pca module 1 i/o cex2 (p1.5): capture/compare external i/o for pca module 2 i/o cex3 (p1.6): capture/compare external i/o for pca module 3 i/o ss (p1.7): slave select input of the spi controller cex4: capture/compare external i/o for pca module 3 xtal1 i input to the inverting oscillator amplifier xtal2 o output from the inverting oscillator amplifier rst/ vpp i rst : negative reset input a low on this pin for two machine cycles while the oscillator is running, resets the device. this pin will include a pull-down to reset the circuit if no external reset level is applied. vpp: high voltage input for otp programming p3.0 - p3.7 i/o port 3 : port 3 is a 8-bit programmable i/o port with internal pull-up. i/o p3.0: programmable as output with push-pull. i/o p3.1: programmable as output with push-pull. i/o dig0 (p3.2): programmable as output with push-pull. int0 : external interrupt 0 i/o p3.3: programmable as output with push-pull. int1 : external interrupt 1 i/o dig1 (p3.4): programmable as output with push-pull. t0: timer 0 external input i/o p3.5: programmable as output with push-pull. t1: timer 1 external input i/o spick (p3.6): clock i/o of the spi controller i/o p3.7: programmable as output with push-pull. p4.0-p4.2 i/o port 4: port 4 is an 3-bit i/o port with internal pull-up 5 at8xc5103 4134c?8051?09/04 clock the errata sheet core needs only 6 clock periods per machine cycle. this feature, called ?x2?, provides the following advantages: ? divides frequency crystals by 2 (cheap er crystals) while keeping the same cpu power. ? saves power consumption while keeping the same cpu power (oscillator power saving). ? saves power consumption by dividing dynamic operating frequency by 2 in operating and idle modes. ? increases cpu power by 2 while keeping the same crystal frequency. in order to keep the original c51 compatibi lity, a divider-by-2 is inserted between the xtal1 signal and the main clock input of the core (phase generator). this divider may be disabled by the software. description the clock for the whole circuit and peripheral is first divided by 2 before being used by the cpu core and peripherals. this allows any cyclic ratio to be accepted on the xtal1 input. in x2 mode, as this divider is bypass ed, the signals on xtal1 must have a cyclic ratio between 40 to 60%. figure 1. shows the clock generation block diagram. the x2 bit is validated on the xtal1 2 rising edge to avoid glitches when switching from the x2 to the std mode. figure 2 shows the mode switching waveforms. 6 at8xc5103 4134c?8051?09/04 figure 1. clock cpu generation diagram xtal1 xtal2 pd pcon.1 1 0 2 fclk_periph peripheral x2 ckcon.0 ckcon0.7 ckcon0.6 pcax2 ckcon0.5 ckcon0.4 ckcon0.3 t1x2 ckcon0.2 t0x2 ckcon0.1 idl pcon.0 1 0 2 1 0 2 1 0 2 1 0 2 x2 ckcon0.0 fspi clock fpca clock ft1 clock ft0 clock fcpu ckcon1.7 ckcon1.6 ckcon1.5 ckcon1.4 ckcon1.3 ckcon1.2 ckcon1.1 spix2 ckcon1.0 clock symbol 7 at8xc5103 4134c?8051?09/04 figure 2. mode switching waveforms the x2 bit in the ckcon register (see table 1) allows switching from 12 clock cycles per instruction to 6 clock cycles and vice versa. at reset, the standard speed is activated (std mode). setting this bit acti vates the x2 feature (x2 mode). note: in order to prevent any incorrect operation while operating in the x2 mode, users must be aware that all peripherals using the clock frequency as a time reference (timers, pca, spi) will have their time reference divided by 2. for example, a free running timer gener- ating an interrupt every 20 ms will th en generate an interrupt every 10 ms. xtal2 xtal1 cpu clock x2 bit x2 mode std mode std mode 8 at8xc5103 4134c?8051?09/04 registers table 1. ckcon0 register ckcon0 (s:8fh) clock control register note: 1. this control bit is validated when the cpu clock bit x2 is set; when x2 is low, this bit has no effect. reset value = xx0x x000b 76543210 pcax2 t1x2 t0x2 x2 bit number bit mnemonic description 7? reserved the value read from this bit is i ndeterminate. do not set this bit. 6? reserved the value read from this bit is i ndeterminate. do not set this bit. 5 pcax2 programmable counter array clock (1) clear to select 6 clock peri ods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 4? reserved the value read from this bit is i ndeterminate. do not set this bit. 3? reserved the value read from this bit is i ndeterminate. do not set this bit. 2t1x2 timer1 clock (1) clear to select 6 clock peri ods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 1t0x2 timer0 clock (1) clear to select 6 clock peri ods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 0x2 cpu clock clear to select 12 clock periods per machine cycle (std mode) for cpu and all the peripherals. set to select 6 clock periods per ma chine cycle (x2 mode) and to enable the individual peripherals "x2" bits. 9 at8xc5103 4134c?8051?09/04 table 2. ckcon1 register ckcon1 (s:afh) clock control register note: 1. this control bit is validated when the cpu clock bit x2 is set; when x2 is low, this bit has no effect. reset value = xxxx xxx0b 76543210 spix2 bit number bit mnemonic description 7? reserved the value read from this bit is i ndeterminate. do not set this bit. 6? reserved the value read from this bit is i ndeterminate. do not set this bit. 5? reserved the value read from this bit is i ndeterminate. do not set this bit. 4? reserved the value read from this bit is i ndeterminate. do not set this bit. 3? reserved the value read from this bit is i ndeterminate. do not set this bit. 2? reserved the value read from this bit is i ndeterminate. do not set this bit. 1? reserved the value read from this bit is i ndeterminate. do not set this bit. 0 spix2 spi clock (1) clear to select 6 clock peri ods per peripheral clock cycle. set to select 12 clock periods per peripheral clock cycle. 10 at8xc5103 4134c?8051?09/04 sfr mapping the special function registers (sfrs) of the at8xc5103 bel ong to the following categories: ? c51 core registers: acc, b, dph, dpl, psw, sp, auxr1 ? i/o port registers: p1, p3 , p4, p1m1, p1m2, p3m1, p3m2 ? timer registers: tcon, th0, th1, tmod, tl0, tl1 ? power and clock control regi sters: ckcon0, ckcon1, pcon ? interrupt system registers: ie , ie1, ipl0, ipl1, iph0, iph1 ? spi: spcon, spsta, spdat ? pca: ccap0l, ccap1l, ccap2l, ccap3l, ccap4l, ccap0h, ccap1h, ccap2h, ccap3h, ccap4h, ccapm 0, ccapm1, ccapm2, ccapm3, ccapm4, cl, ch, cmod, ccon 11 at8xc5103 4134c?8051?09/04 reserved table 3. sfr addresses and reset values 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f f8h ch 0000 0000 ccap0h 0000 0000 ccap1h 0000 0000 ccap2h 0000 0000 ccap3h 0000 0000 ccap4h 0000 0000 ffh f0h b 0000 0000 f7h e8h cl 0000 0000 ccap0l 0000 0000 ccap1l 0000 0000 ccap2l 0000 0000 ccap3l 0000 0000 ccap4l 0000 0000 efh e0h acc 0000 0000 p1m2 0000 0000 p3m2 0000 0000 e7h d8h ccon 00x0 0000 cmod 00xx x000 ccapm0 x000 0000 ccapm1 x000 0000 ccapm2 x000 0000 ccapm3 x000 0000 ccapm4 x000 0000 df h d0h psw 0000 0000 p1m1 0000 0000 p3m1 0000 0000 d7h c8h cf h c0h p4 xxxx x111 spcon 0001 0100 spsta 00x0 xxxx spdat xxxx xxxx c7h b8h ipl0 x0xx 0000 bfh b0h p3 1111 1111 ie1 xxxx x0xx ipl1 xxxx x0xx iph1 xxxx x0xx iph0 x0xx 0000 b7h a8h ie0 00xx 0000 ckcon1 xxxx xxx0 afh a0h auxr1 xxxxx0x0 a7h 98h 9fh 90h p1 1111 1111 97h 88h tcon 0000 0000 tmod 0000 0000 tl0 0000 0000 tl1 0000 0000 th0 0000 0000 th1 0000 0000 ckcon0 xx0x x000b 8fh 80h sp 0000 0111 dpl 0000 0000 dph 0000 0000 pcon xxx1 0000 87h 0/8 1/9 2/a 3/b 4/c 5/d 6/e 7/f 12 at8xc5103 4134c?8051?09/04 ports the at8xc5103 has 3 i/o ports, port 1, port 3 and port 4. except rst , and port 4, all port 1 and port 3 i/o port pins on the at8xc5103 may be software configured to one of four types on a bit-by-bit basis, as shown in table 2 these are: quasi-bi-directional (standard 80c51 port outputs), push-pull, open drain, and input only. two configuration registers for each port choose the output type for each port pin. port types quasi-bi-directional output configuration the default port output configuration for standard at8xc5103 i/o ports is the quasi-bi- directional output that is common on the 80c51 and most of its derivatives. this output type can be used as both an input and output without the need to reconfigure the port. this is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. when th e pin is pulled low, it is driven strongly and able to sink a fairly large current. these f eatures are somewhat similar to an open drain output except that there are three pull-up transistors in the quasi-bi-directional output that serve different purposes. one of these pull-ups, called the ?very weak? pull-up, is turned on whenever the port latch for the pin contains a logic 1. the very weak pull-up sources a very small current that will pull the pin high if it is left floating. a second pull- up, called the ?weak? pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. this pull-up provides the primary source cur- rent for a quasi-bi-directional pi n that is outputting a 1. if a pin that has a logic 1 on it is pulled low by an external device, the weak pull-up turns off, and only the very weak pull- up remains on. in order to pull the pin low under these conditions, the external device has to sink enough current to overpower the weak pull-up and take the voltage on the port pin below it s input threshold. the third pull-up is referred to as the ?strong? pull-up. this pull-up is used to speed up low-to-high transitions on a quasi-bi-directional port pin when the port latch changes from a logic 0 to a logic 1. when this occurs, the strong pull-up turns on for a brief time, two cpu clocks, in order to pull the port pin high quickly. then it turns off again. the quasi-bi-directional port configuration is shown in figure 3. pxm1.y bit pxm2.y bit port output mode 0 0 quasi bi-directional 0 1 push-pull 1 0 input only (high impedance) 1 1 open drain 13 at8xc5103 4134c?8051?09/04 figure 3. quasi-bi-directional output open drain output configuration the open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latc h contains a logic 0. to be used as a logic output, a port configured in this manner must have an external pull-up, typically a resis- tor tied to v dd . the pull-down for this mode is the same as for the quasi-bi-directional mode. the open drain port configuration is shown in figure 4. figure 4. open drain output push-pull output configuration the push-pull output configuration has the same pull-down struct ure as both the open drain and the quasi-bi-directional output modes, but provides a continuous strong pull- up when the port latch contains a logic 1. the push-pull mode may be used when more source current is needed from a port output. the push-pull port configuration is shown in figure 5. figure 5. push-pull output 2 cpu input pin strong very weak n p p weak p clock delay port latch data data input pin n port latch data data input pin strong n p port latch data data 14 at8xc5103 4134c?8051?09/04 input only configuration the input only configuration is a pure input with neither pull-up nor pull-down. the input only configuration is shown in figure 6. figure 6. input only ports description ports p1 and p3 the inputs of each i/o port of the at8xc5103 are ttl level schmitt triggers with hysteresis. registers table 4. p1m1 register p1m1 address (d4h) reset value = 0000 0000 table 5. p1m2 register p1m2 address (e2h) reset value = 0000 0000 input pin data 76543210 p1m1.7 p1m1.6 p1m1.5 p1m1.4 p1m1.3 p1m1.2 p1m1.1 p1m1.0 bit number bit mnemonic description 0-7 p1m1.x port output configuration bit see table 2 for configuration definition 76543210 p1m2.7 p1m2.6 p1m2.5 p1m2.4 p1m2.3 p1m2.2 p1m2.1 p1m2.0 bit number bit mnemonic description 0-7 p1m2.x port output configuration bit see table 2 for configuration definition 15 at8xc5103 4134c?8051?09/04 table 6. p3m1 register p3m1 address (d5h) reset value = 0000 0000 table 7. p3m2 register p3m2 address (e4h) reset value = 0000 0000 76543210 p3m1.7 p3m1.6 p3m1.5 p3m1.4 p3m1.3 p3m1.2 p3m1.1 p3m1.0 bit number bit mnemonic description 0-7 p3m1.x port output configuration bit see table 2 for configuration definition 76543210 p3m2.7 p3m2.6 p3m2.5 p3m2.4 p3m2.3 p3m2.2 p3m2.1 p3m2.0 bit number bit mnemonic description 0-7 p3m2.x port output configuration bit see table 2 for configuration definition 16 at8xc5103 4134c?8051?09/04 dual-data pointer register (dptr) the additional data pointer can be used to speed up code exec ution and reduce code size in a number of ways. the dual dptr structure is a way by which the device will specify the address of an external data memory location. there are tw o 16-bit dptr registers that address the external memory, and a single bit called dps = auxr1/bit0 (see table 8) that allows the program code to switch between them (refer to figure 7). figure 7. use of dual-data pointer table 8. auxr1: auxiliary register 1 reset value = xxxx x0x0 note: 1. user software should not write 1s to re served bits. these bits may be used in future 8051 family products to invoke new features. in that case, the reset value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. e x t erna l d a t a m emory auxr1(a2h) dps dph(83h) dpl(82h) 0 7 dptr0 dptr1 76543210 -----0-dps bit number bit mnemonic description 7-3 - reserved (1) the value read from this bit is i ndeterminate. do not set this bit. 2 0 always stuck at 0 1- reserved the value read from this bit is i ndeterminate. do not set this bit. 0dps data pointer selection clear to select dptr0. set to select dptr1. 17 at8xc5103 4134c?8051?09/04 application software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operat ions (copy, compare, search...) are well served by using one data pointer as a ?source? pointer a nd the other one as a "destina- tion" pointer. assembly language ; block move using dual data pointers ; destroys dptr0, dptr1, a and psw ; note: dps exits opposite of entry state ; unless an extra inc auxr1 is added ; 00a2 auxr1 equ 0a2h ; 0000 909000mov dptr,#source ; address of source 0003 05a2 inc auxr1 ; switch data pointers 0005 90a000 mov dptr,#dest ; address of dest 0008 loop: 0008 05a2 inc auxr1 ; switch data pointers 000a e0 movx a,@dptr ; get a byte from source 000b a3 inc dptr ; increment source address 000c 05a2 inc auxr1 ; switch data pointers 000e f0 movx @dptr,a ; write the byte to dest 000f a3 inc dptr ; increment dest address 0010 70f6jnz loop ; check for 0 terminator 0012 05a2 inc auxr1 ; (optional) restore dps inc is a short (2 bytes) and fast (12 clocks) way to manipulate the dps bit in the auxr1 sfr. however, note that the inc instruction does not directly force the dps bit to a par- ticular state, but simply toggl es it. in simple routines, su ch as the block move example, only the fact that dps is togg led in the proper sequence matters, not its actual value. in other words, the block move routine works the same whether dps is ?0? or ?1? on entry. observe that without the last instruction (i nc auxr1), the routine will exit with dps in the opposite state. 18 at8xc5103 4134c?8051?09/04 serial port interface (spi) the serial peripheral interface module (spi) which allows full-duplex, synchronous, serial communication between the mcu and peripheral devices, including other mcus. features features of the spi module include the following: ? full-duplex, three-wire synchronous transfers ? master or slave operation ? eight programmable master clock rates ? serial clock with programmable polarity and phase ? master mode fault error flag with mcu interrupt capability ? write collision flag protection signal description figure 8 shows a typical spi bus configurat ion using one master controller and many slave peripherals. the bus is made of three wires connecting all the devices. figure 8. typical spi bus the master device selects the individual slav e devices by using four pins of a parallel port to control the four ss pins of the slave devices. master output slave input (mosi) this 1-bit signal is directly connected be tween the master device and a slave device. the mosi line is used to transfer data in se ries from the master to the slave. therefore, it is an output signal from the master, and an input signal to a slave. a byte (8-bit word) is transmitted most significant bit (msb) first, least significant bit (lsb) last. master input slave output (miso) this 1-bit signal is directly connected be tween the slave device and a master device. the miso line is used to transfer data in se ries from the slave to the master. therefore, it is an output signal from t he slave, and an input signal to the master. a byte (8-bit word) is transmitted mo st significant bit (msb) first, least significant bit (lsb) last. spi serial clock (sck) this signal is used to synchronize the data movement both in and out the devices through their mosi and miso lines. it is dr iven by the master for eight clock cycles which allows to exchange one byte on the serial lines. slave 1 miso mosi sck ss miso mosi sck ss port 0 1 2 3 slave 3 miso mosi sck ss slave 4 miso mosi sck ss slave 2 miso mosi sck ss v dd master 19 at8xc5103 4134c?8051?09/04 slave select (ss ) each slave peripheral is selected by one slave select pin (ss ). this signal must stay low for any message for a slave. it is obvious that only one master (ss high level) can drive the network. the master may select each slave device by software through port pins (figure 8). to prevent bus conflicts on the miso line, only one slave should be selected at a time by the master for a transmission. in a master configuration, the ss line can be used in conjun ction with the modf flag in the spi status register (spsta) to prevent multiple masters from driving mosi and sck (see error conditions). a high level on the ss pin puts the miso line of a slav e spi in a high-impedance state. the ss pin could be used as a general purpose if the following conditions are met: ? the device is configured as a master and the ssdis control bit in spcon is set. this kind of configuration can be found when only one master is driving the network and there is no way that the ss pin will be pulled low. ther efore, the modf flag in the spsta will never be set (1) . ? the device is configured as a slav e with cpha and ssdis control bits set (2) . this kind of configuration can happen when the system comprises one master and one slave only. therefore, the device should a lways be selected and there is no reason that the master uses the ss pin to select the communicating slave device. baud rate in master mode, the baud rate can be selected from a baud rate generator which is con- trolled by three bits in the spcon regist er: spr2, spr1 and spr0. the master clock is chosen from one of six clock ra tes resulting from the division of the internal clock by 4, 8, 16, 32, 64 or 128. table 9 gives the different clock rates selected by spr2:spr1:spr0: 1. clearing ssdis control bit does not clear modf. 2. special care should be taken not to set ssdis control bit when cpha = ?0? because in this mode, the ss is used to start the transmission. table 9. spi master baud rate selection spr2:spr1:spr0 clock rate baud rate divisor (bd) 000 don?t use no brg 001 f clk_periph /4 4 010 f clk_periph /8 8 011 f clk_periph /16 16 100 f clk_periph /32 32 101 f clk_periph /64 64 110 f clk_periph /128 128 111 don?t use no brg 20 at8xc5103 4134c?8051?09/04 functional description figure 9 shows a detailed structure of the spi module. figure 9. spi module block diagram operating modes the serial peripheral interface can be configured as one of the two modes: master mode or slave mode. the configuration and initialization of the spi module is made through one register: ? the serial peripheral control register (spcon) once the spi is configured, the data exchange is made using: ? spcon ? the serial peripheral status register (spsta) ? the serial peripheral data register (spdat) during an spi transmission, data is simultane ously transmitted (shifted out serially) and received (shifted in serially). a serial cloc k line (sck) synchronizes shifting and sam- pling on the two serial data lines (mos i and miso). a slave select line (ss ) allows individual selection of a slave spi device; slave devices that are not selected do not interfere with spi bus activities. when the master device transmits data to t he slave device via the mosi line, the slave device responds by sending data to the master device via the miso line. this implies full-duplex transmission with both data out and data in synchronized with the same clock (figure 10). shift register 0 1 2 3 4 5 6 7 internal bus pin control logic miso mosi sck m s clock logic clock divider clock select /4 /64 /128 spi interrupt request 8-bit bus 1-bit signal ss intclk /32 /8 /16 receive data register spdat spi control spsta cpha spr0 spr1 cpol mstr ssdis spen spr2 spcon wcol modf spif - ---- 21 at8xc5103 4134c?8051?09/04 figure 10. full-duplex master-slave interconnection master mode the spi operates in master mode when the master bit, mstr (1) , in the spcon register is set. only one master spi device can initiate transmissions. software begins the trans- mission from a master spi module by writin g to the serial peripheral data register (spdat). if the shift register is empty, th e byte is immediately transferred to the shift register. the byte begins shifting out on mosi pin under the control of the serial clock, sck. simultaneously, another byte shifts in from the slave on the master?s miso pin. the transmission ends when the serial pe ripheral transfer data flag, spif, in spsta becomes set. at the same time that spif beco mes set, the received byte from the slave is transferred to the receive data register in spdat. software clears spif by reading the serial peripheral status register (spsta) with the spif bit set, and then reading the spdat. when the pin ss is pulled down during a transmission, the data is interrupted and when the transmission is established again, the data present in the spdat is resent. slave mode the spi operates in slave mode when the master bit, mstr (2) , in the spcon register is cleared. before a data transmission occurs, the slave select pin, ss , of the slave device must be set to ?0?. ss must remain low until th e transmission is complete. in a slave spi module, data enters the shift register under the control of the sck from the master spi module. after a byte enters the shift register, it is immediately transferred to the receive data register in spdat, and the spif bit is set. to prevent an overflow condition, slave software must then read the spdat before another byte enters the shift register (3) . a slave spi must complete the writ e to the spdat (s hift register) at least one bus cycle before the master spi starts a transmission. if the write to the data register is late, the spi transmits the data al ready in the shift register from the previous transmission. transmission formats software can select any of four combinati ons of serial clock (sck) phase and polarity using two bits in the spcon: the clock polarity (cpol (4) ) and the clock phase (cpha (4) ). cpol defines the default sck line leve l in idle state. it has no significant effect on the transmission format. cpha de fines the edges on which the input data are sampled and the edges on which the output data are shifted (figure 11 and figure 12). the clock phase and polarity should be ident ical for the master spi device and the com- municating slave device. 8-bit shift register spi clock generator master mcu 8-bit shift register miso miso mosi mosi sck sck vss v dd ss ss slave mcu 1. the spi module should be configured as a master before it is enabled (spen set). also the master spi should be configured before the slave spi. 2. the spi module should be configured as a slave before it is enabled (spen set). 3. the maximum frequency of the sck for an spi configured as a slave is the bus clock speed. 4. before writing to the cpol and cpha bits , the spi should be disa bled (spen = "0"). 22 at8xc5103 4134c?8051?09/04 figure 11. data transmission format (cpha = 0) figure 12. data transmission format (cpha = 1) as shown in figure 11, the first sck edge is the msb capture strobe. therefore, the slave must begin drivin g its data before the first sck edge, and a falling edge on the ss pin is used to start the transmission. t he ss pin must be toggled high and then low between each byte transmitted (figure 13). figure 13. cpha/ss timing figure 12 shows an spi transmission in whic h cpha is ?1?. in this case, the master begins driving its mosi pin on the first sck edge. therefore the slave uses the first sck edge as a start transmission signal. th e ss pin can remain low between transmis- sions (figure 13). this format may be preferab le in systems having only one master and only one slave driving the miso data line. msb bit6 bit5 bit4 bit3 bit2 bit1 lsb bit6 bit5 bit4 bit3 bit2 bit1 msb lsb 13 245678 capture point ss (to slave) miso (from slave) mosi (from master) sck (cpol = 1) sck (cpol = 0) spen (internal) sck cycle number msb bit6 bit5 bit4 bit3 bit2 bit1 lsb bit6 bit5 bit4 bit3 bit2 bit1 msb lsb 13 245678 capture point ss (to slave) miso (from slave) mosi (from master) sck (cpol = 1) sck (cpol = 0) spen (internal) sck cycle number byte 1 byte 2 byte 3 miso/mosi master ss slave ss (cpha = 1) slave ss (cpha = 0) 23 at8xc5103 4134c?8051?09/04 error conditions the following flags in the spsta signal spi error conditions. mode fault (modf) mode fault error in master mode spi indicate s that the level on the slave select (ss ) pin is inconsistent with the actual mode of the device. modf is set to warn that there may have a multi-master conflict for system control. in this case, the spi system is affected in the following ways: ? an spi receiver/error cpu interrupt request is generated. ? the spen bit in spcon is cl eared. this disable the spi. ? the mstr bit in spcon is cleared. when ss disable (ssdis) bit in the spcon r egister is cleared, the modf flag is set when the ss signal becomes ?0?. however, as stated before, for a system with one master, if the ss pin of the master device is pulled low, there is no way that an other master is attempting to drive the net- work. in this case, to prevent the modf flag from being set, soft ware can set the ssdis bit in the spcon register and therefore maki ng the ss pin as a general-purpose i/o pin. clearing the modf bit is ac complished by a read of spsta register with modf bit set, followed by a write to the spcon register. spen control bit may be re stored to its orig- inal set state after the modf bit has been cleared. write collision (wcol) a write collision (wcol) flag in the spsta is set when a write to the spdat register is done during a transmit sequence. wcol does not cause an interruption, and the transfer continues uninterrupted. clearing the wcol bit is done through a software sequence of an access to spsta and an access to spdat. overrun condition an overrun condition occurs when the master device tries to send several data bytes and the slave device has not cleared the spif bit issuing from the previous data byte transmitted. in this case, the receiver buffer contains the by te sent after the spif bit was last cleared. a read of the spdat return s this byte. all others bytes are lost. this condition is not detected by the spi peripheral. ss error flag (sserr) a synchronous serial slave error occurs when ss goes high before the end of a received data in slave mode. sserr does not cause in interruption, this bit is cleared by writing 0 to spen bit (reset of the spi state machine). interrupts two spi status flags can generate a cpu interrupt requests (see table 10) table 10. spi interrupts serial peripheral data transf er flag, spif: this bit is se t by hardware when a transfer has been completed. spif bit generates transmitter cpu interrupt requests. mode fault flag, modf: this bit becomes se t to indicate that the level on the ss is inconsistent with the mode of the spi. modf with ssdis reset, generates receiver/error cpu interrupt requests. figure 14 gives a logical view of the above statements. flag request spif (sp data transfer) spi transmitter interrupt request modf (mode fault) spi receiver/error interrupt request (if ssdis = "0") 24 at8xc5103 4134c?8051?09/04 figure 14. spi interrupt requests generation registers there are three registers in the module that provide control, status and data storage functions. these registers are describes in the following paragraphs. serial peripheral control register (spcon) the serial peripheral control register does the following: ? selects one of the master clock rates ? configure the spi module as master or slave ? selects serial clock polarity and phase ? enables the spi module ? frees the ss pin for a general purpose table 11 describes this register a nd explains the use of each bit. ssdis modf cpu interrupt request spi receiver/error cpu interrupt request spi transmitter spi cpu interrupt request spif table 11. spcon register: serial peripheral control register - spcon (s:c3h) 76543210 spr2 spen ssdis mstr cpol cpha spr1 spr0 bit number bit mnemonic r/w mode description 7 spr2 r/w serial peripheral rate 2 bit with spr1 and spr0 define the clock rate 6spenr/w serial peripheral enable clear to disable the spi interface (internal reset of the spi) set to enable the spi interface 5 ssdis r/w ss disable clear to enable ss in both master and slave modes set to disable ss in both master and slave modes. in slave mode, this bit has no effect if cpha = "0" 4mstrr/w serial peripheral master clear to configure the spi as a slave set to configure the spi as a master 3cpolr/w clock polarity clear to have the sck set to ?0? in idle state set to have the sck set to ?1? in idle low 2cphar/w clock phase clear to have the data sampled when the spsck leaves the idle state (see cpol) set to have the data sampled when the spsck returns to idle state (see cpol) 1 spr1 r/w serial peripheral rate (spr2:spr1:spr0) 000: n.a. 001: f clk periph /4 010: f clk periph /8 011: f clk periph /16 25 at8xc5103 4134c?8051?09/04 reset value = 00010100b serial peripheral status register (spsta) the serial peripheral status register contai ns flags to signal th e following conditions: ? data transfer complete ? write collision ? inconsistent logic level on ss pin (mode fault error) table 12 describes the spsta register and expl ains the use of every bit in the register. reset value = 00x0xxxxb 0 spr0 r/w 100: f clk periph /32 101: f clk periph /64 110: f clk periph /128 111: don?t use bit number bit mnemonic r/w mode description table 12. spsta: serial peripheral status an d control register - spsta (s:c4h) 76543210 spif wcol sserr modf - - - - bit number bit mnemonic r/w mode description 7 spif r serial peripheral data transfer flag clear by hardware to indicate data transfer is in progress or has been approved by a clearing sequence. set by hardware to indicate that the data transfer has been completed. 6wcolr write collision flag cleared by hardware to indicate that no collisi on has occurred or has been approved by a clearing sequence. set by hardware to indicate t hat a collision has been detected. 5 sserr r synchronous serial slave error flag set by hardware when ss is deasserted before the end of a received data. cleared by disabling the spi (clearing spen bit in spcon). 4modfr mode fault cleared by hardware to indicate that the ss pin is at appropriate logic level, or has been approved by a clearing sequence. set by hardware to indicate that the ss pin is at inappropriate logic level 3-r/w reserved the value read from this bit is i ndeterminate. do not set this bit. 2-r/w reserved the value read from this bit is i ndeterminate. do not set this bit. 1-r/w reserved the value read from this bit is i ndeterminate. do not set this bit. 0-r/w reserved the value read from this bit is i ndeterminate. do not set this bit. 26 at8xc5103 4134c?8051?09/04 serial peripheral data register (spdat) the serial peripheral data register (table 13) is a read/write buffer for the receive data register. a write to spdat plac es data directly into the shif t register. no transmit buffer is available in this model. a read of the spdat returns the value locat ed in the receive buffer and not the content of the shift register. table 13. spdat (s:c5h): serial peripheral data register reset value = xxxx xxxxb r7:r0: receive data bits spcon, spsta and spdat registers may be r ead and written at any time while there is no on-going exchange. however, special care should be taken when writing to them while a transmission is on-going: ? do not change spr2, spr1 and spr0 ? do not change cpha and cpol ? do not change mstr ? clearing spen would immediat ely disable the peripheral ? writing to the spdat will cause an overflow 76543210 r7 r6 r5 r4 r3 r2 r1 r0 27 at8xc5103 4134c?8051?09/04 timers/counters the errata sheet implements two general-purpose, 16-bit timers/counters. they are identified as timer 0 and timer 1, and can be independently configured to operate in a variety of modes as a timer or as an event counter. when operating as a timer, the timer/counter runs for a programmed length of time, then issues an interrupt request. when operating as a counter, the timer/counter counts negative transitions on an external pin. after a preset number of counts, the counter issues an interrupt request. the various operating modes of each time r/counter are described in the following sections. timer/counter operations for instance, a basic operation is timer regi sters thx and tlx (x = 0, 1) connected in cascade to form a 16-bit timer. setting the run control bit (trx) in tcon register (see figure 14) turns the timer on by allowing t he selected input to increment tlx. when tlx overflows it increments thx; when thx overflows it sets the timer overflow flag (tfx) in tcon register. setting the trx does not clear the thx and tlx timer registers. timer registers can be accessed to obtain the current count or to enter preset values. they can be read at any time but trx bit must be cleared to preset their values, other/wise the behavior of the timer/counter is unpredictable. the c/tx# control bit selects timer operati on or counter operation by selecting the divided-down peripheral clock or external pin tx as the source for the counted signal. trx bit must be cleared when changing the mode of operation, other/wise the behavior of the timer/counter is unpredictable. for timer operation (c/tx# = 0), the timer register counts the divided-down peripheral clock. the timer register is incremented once every peripheral cycle (6 peripheral clock periods). the timer clock rate is f per /6, i.e. f osc /12 in standard mode or f osc /6 in x2 mode. for counter operation (c/tx# = 1), the timer register counts the negative transitions on the tx external input pin. the external in put is sampled every peripheral cycles. when the sample is high in one cycle and low in the next one, the counter is incremented. since it takes 2 cycles (12 peripheral clock pe riods) to recognize a negative transition, the maximum count rate is f per /12, i.e. f osc /24 in standard mode or f osc /12 in x2 mode. there are no restrictions on the duty cycle of the ex ternal input signal, but to ensure that a given level is sampled at leas t once before it changes, it should be held for at least one full peripheral cycle. timer 0 timer 0 functions as either a timer or event counter in four modes of operation. figure 15 through figure 18 show the lo gical configuration of each mode. timer 0 is controlled by the fo ur lower bits of tmod register (see figure 15) and bits 0, 1, 4 and 5 of tcon register (see figure 14). tmod register selects the method of timer gating (gate0), timer or counter operation (t/c0#) and mode of operation (m10 and m00). tcon register provides timer 0 control functions: overflow flag (tf0), run control bit (tr0), interrupt flag (ie0) and interrupt type control bit (it0). for normal timer operation (gate0 = 0), setting tr0 allows tl0 to be incremented by the selected input. setting gate0 and tr0 allows external pin int0# to control timer operation. timer 0 overflow (count rolls over from all 1s to all 0s) sets tf0 flag generating an inter- rupt request. it is important to stop time r/counter before changing mode. 28 at8xc5103 4134c?8051?09/04 mode 0 (13-bit timer) mode 0 configures timer 0 as an 13-bit timer which is set up as an 8-bit timer (th0 register) with a modulo 32 prescaler implemente d with the lower five bits of tl0 register (see figure 15). the upper three bits of tl0 register are indeterminate and should be ignored. prescaler overflow increments th0 register. figure 15. timer/counter x (x = 0 or 1) in mode 0 mode 1 (16-bit timer) mode 1 configures timer 0 as a 16-bit timer with th0 and tl0 registers connected in cascade (see figure 16). the selected input increments tl0 register. figure 16. timer/counter x (x = 0 or 1) in mode 1 mode 2 (8-bit timer with auto- reload) mode 2 configures timer 0 as an 8-bit time r (tl0 register) that automatically reloads from th0 register (see figure 17). tl0 overflow sets tf0 flag in tcon register and reloads tl0 with the contents of th0, which is preset by software. when the interrupt request is serviced, hardware clears tf0. the reload leaves th0 unchanged. the next reload value may be changed at any time by writing it to th0 register. figure 17. timer/counter x (x = 0 or 1) in mode 2 periph clock trx tcon reg tfx tcon reg 0 1 gatex tmod reg 6 overflow timer x interrupt request c/tx# tmod reg tlx (5 bits) thx (8 bits) intx# tx trx tcon reg tfx tcon reg 0 1 gatex tmod reg overflow timer x interrupt request c/tx# tmod reg tlx (8 bits) thx (8 bits) intx# tx periph clock 6 trx tcon reg tfx tcon reg 0 1 gatex tmod reg overflow timer x interrupt request c/tx# tmod reg tlx (8 bits) thx (8 bits) intx# tx periph clock 6 29 at8xc5103 4134c?8051?09/04 mode 3 (two 8-bit timers) mode 3 configures timer 0 such that registers tl0 and th0 operate as separate 8-bit timers (see figure 18). this mode is provided for applications requiring an additional 8- bit timer or counter. tl0 uses the timer 0 control bits c/t0# and gate0 in tmod reg- ister, and tr0 and tf0 in tcon register in the normal manner. th0 is locked into a timer function (counting f per /6) and takes over use of the timer 1 interrupt (tf1) and run control (tr1) bits. thus, operation of ti mer 1 is restricted when timer 0 is in mode 3. figure 18. timer/counter 0 in mode 3: two 8-bit counters timer 1 timer 1 is identical to timer 0 excepted for mode 3 which is a hold-count mode. the fol- lowing comments help to understand the differences: ? timer 1 functions as either a timer or event counter in three modes of operation. figure 15 through figure 17 show the logical configuration for modes 0, 1, and 2. timer 1?s mode 3 is a hold-count mode. ? timer 1 is controlled by the four high-ord er bits of tmod register (see figure 15) and bits 2, 3, 6 and 7 of tcon register (see figure 14). tmod register selects the method of timer gating (gate1), timer or counter operation (c/t1#) and mode of operation (m11 and m01). tcon register provides timer 1 control functions: overflow flag (tf1), run control bit (tr1), interrupt flag (ie1) and interrupt type control bit (it1). ? timer 1 can serve as the baud rate generator for the serial port. mode 2 is best suited for this purpose. ? for normal timer operation (gate1 = 0), setting tr1 allows tl1 to be incremented by the selected input. setting gate1 and tr 1 allows external pin int1# to control timer operation. ? timer 1 overflow (count rolls over from all 1s to all 0s) sets the tf1 flag generating an interrupt request. ? when timer 0 is in mode 3, it uses timer 1?s overflow flag (tf1) and run control bit (tr1). for this situation, use timer 1 only for applications that do not require an interrupt (such as a baud rate generator for the serial port) and switch timer 1 in and out of mode 3 to turn it off and on. ? it is important to stop timer/counter before changing mode. tr0 tcon.4 tf0 tcon.5 int0 # 0 1 gate0 tmod.3 overflow timer 0 interrupt request c/t0# tmod.2 tl0 (8 bits) tr1 tcon.6 th0 (8 bits) tf1 tcon.7 overflow timer 1 interrupt request t0 periph clock 6 periph clock 6 30 at8xc5103 4134c?8051?09/04 mode 0 (13-bit timer) mode 0 configures timer 1 as a 13-bit timer, which is set up as an 8-bit timer (th1 reg- ister) with a modulo-32 prescaler implemented with the lower 5 bits of the tl1 register (see figure 15). the upper 3 bits of tl1 regist er are ignored. prescaler overflow incre- ments th1 register. mode 1 (16-bit timer) mode 1 configures timer 1 as a 16-bit timer with th1 and tl1 registers connected in cascade (see figure 16). the selected input increments tl1 register. mode 2 (8-bit timer with auto- reload) mode 2 configures timer 1 as an 8-bit timer (tl1 register) with automatic reload from th1 register on overflow (see figure 17). tl 1 overflow sets tf1 flag in tcon register and reloads tl1 with the contents of th1, which is preset by software. the reload leaves th1 unchanged. mode 3 (halt) placing timer 1 in mode 3 causes it to halt and hold its count. this can be used to halt timer 1 when tr1 run control bit is not av ailable i.e. when timer 0 is in mode 3. interrupt each timer handles one interrupt source that is the timer overflow flag tf0 or tf1. this flag is set every time an overflow occurs. flags are cleared when vectoring to the timer interrupt routine. interrupts are enabled by setting etx bit in ie0 register. this assumes interrupts are globally enabled by setting ea bit in ie0 register. figure 19. timer interrupt system tf0 tcon.5 et0 ie0.1 timer 0 interrupt request tf1 tcon.7 et1 ie0.3 timer 1 interrupt request 31 at8xc5103 4134c?8051?09/04 registers table 14. tcon register tcon (s:88h) timer/counter control register reset value = 0000 0000b 76543210 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 bit number bit mnemonic description 7tf1 timer 1 overflow flag cleared by hardware when processor vectors to interrupt routine. set by hardware on timer/counter overflow, when timer 1 register overflows. 6tr1 timer 1 run control bit clear to turn off timer/counter 1. set to turn on timer/counter 1. 5tf0 timer 0 overflow flag cleared by hardware when processor vectors to interrupt routine. set by hardware on timer/counter overflow, when timer 0 register overflows. 4tr0 timer 0 run control bit clear to turn off timer/counter 0. set to turn on timer/counter 0. 3ie1 interrupt 1 edge flag cleared by hardware when interrupt is processed if edge-triggered (see it1). set by hardware when external interrupt is detected on int1# pin. 2it1 interrupt 1 type control bit clear to select low level active (level triggered) for external interrupt 1 (int1#). set to select falling edge active ( edge triggered) for external interrupt 1. 1ie0 interrupt 0 edge flag cleared by hardware when interrupt is processed if edge-triggered (see it0). set by hardware when external interrupt is detected on int0# pin. 0it0 interrupt 0 type control bit clear to select low level active (level triggered) for external interrupt 0 (int0#). set to select falling edge active ( edge triggered) for external interrupt 0. 32 at8xc5103 4134c?8051?09/04 reset value = 0000 0000b table 16. th0 register th0 (s:8ch) timer 0 high byte register reset value = 0000 0000b table 15. tmod register tmod (s:89h) timer/counter mode control register 76543210 gate1 c/t1# m11 m01 gate0 c/t0# m10 m00 bit number bit mnemonic description 7gate1 timer 1 gating control bit clear to enable timer 1 whenever tr1 bit is set. set to enable timer 1 only while int 1# pin is high and tr1 bit is set. 6c/t1# timer 1 counter/timer select bit clear for timer operation: timer 1 counts the divided-down system clock. set for counter operation: timer 1 counts negative transitions on external pin t1. 5m11 timer 1 mode select bits m11 m01 operating mode 0 0 mode 0: 8-bit timer/counter (th1) with 5-bit prescaler (tl1). 0 1 mode 1: 16-bit timer/counter. 1 0 mode 2: 8-bit auto-reload timer/counter (tl1). reloaded from th1 at overflow. 1 1 mode 3: timer 1 halted. retains count. 4m01 3gate0 timer 0 gating control bit clear to enable timer 0 whenever tr0 bit is set. set to enable timer/counter 0 only while int0# pin is high and tr0 bit is set. 2c/t0# timer 0 counter/timer select bit clear for timer operation: timer 0 counts the divided-down system clock. set for counter operation: timer 0 counts negative transitions on external pin t0. 1m10 timer 0 mode select bit m10 m00 operating mode 0 0 mode 0: 8-bit timer/counter (th0) with 5-bit prescaler (tl0). 0 1 mode 1: 16-bit timer/counter. 1 0 mode 2: 8-bit auto-reload timer/counter (tl0). reloaded from th0 at overflow. 1 1 mode 3: tl0 is an 8-bit timer/counter. th0 is an 8-bit timer using timer 1?s tr0 and tf0 bits. 0 m00 76543210 bit number bit mnemonic description 7:0 high byte of timer 0 33 at8xc5103 4134c?8051?09/04 table 17. tl0 register tl0 (s:8ah) timer 0 low byte register reset value = 0000 0000b table 18. th1 register th1 (s:8dh) timer 1 high byte register reset value = 0000 0000b table 19. tl1 register tl1 (s:8bh) timer 1 low byte register reset value = 0000 0000b 76543210 bit number bit mnemonic description 7:0 low byte of timer 0 76543210 bit number bit mnemonic description 7:0 high byte of timer 1 76543210 bit number bit mnemonic description 7:0 low byte of timer 1 34 at8xc5103 4134c?8051?09/04 power management table 20. pcon register pcon - power contro l register (87h) reset value = xxx1 0000b not bit addressable idle mode an instruction that sets pcon.0 indicates th at it is the last instruction to be executed before going into the idle mode. in the idle mode, the internal clock signal is gated off to the cpu, but not to the interrupt, timer, and serial port functions. the cpu status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator and all other registers maintain their data during idle. the port pins hold the logical states they had at the time idle was activated. there are two ways to terminate the idle mode. activation of any enabled interrupt will cause pcon.0 to be cleared by hardware, te rminating the idle mode. the interrupt will be serviced, and following reti the next instruction to be executed will be the one fol- lowing the instruction that put the device into idle. the flag bits gf0 and gf1 can be used to give an indication if an interrupt occurred dur- ing normal operation or during an idle. for example, an instruction that activates idle can also set one or both flag bits. when idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. the other way of terminating the idle mode is with a hardware reset. since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator per iods) to comple te the reset. 76543210 ----gf1gf0pdidl bit number bit mnemonic description 7- reserved the value read from this bit is i ndeterminate. do not set this bit. 6- reserved the value read from this bit is i ndeterminate. do not set this bit. 5- reserved the value read from this bit is i ndeterminate. do not set this bit. 4- reserved the value read from this bit is i ndeterminate. do not set this bit. 3gf1 general-purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 2gf0 general-purpose flag cleared by user for general purpose usage. set by user for general purpose usage. 1pd power-down mode bit cleared by hardware when reset occurs. set to enter power-down mode. 0idl idle mode bit cleared by hardware when interrupt or reset occurs. set to enter idle mode. 35 at8xc5103 4134c?8051?09/04 power-down mode to save maximum power, a power-down mode can be invoked by software (refer to table 20, pcon register). in power-down mode, the oscillator is st opped and the instruction that invoked power- down mode is the last instruction executed . the internal ram and sfrs retain their value until the power-down mode is terminated. v cc can be lowered to save further power. either a hardware reset or an external interrupt can cause an exit from power- down. to properly terminate power-down mode, the reset or external interrupt should not be executed before v cc is restored to its normal operating level and must be held active long enough for the o scillator to rest art and stabilize. only external interrupts int0 , int1 are useful for exiting from power-down. for that, interrupt must be enabled and configured as level or edge sensitive interrupt input. holding the pin low restarts the oscillator bu t bringing the pin high completes the exit as detailed in figure 20. when both interrupts ar e enabled, the oscillator restarts as soon as one of the two inpu ts is held low and power-down exit will be completed when the first input is released. in this case the higher pr iority interrupt servic e routine is executed. once the interrupt is serviced, the next instru ction to be executed after reti will be the one following the instruct ion that put at8xc5103 into power-down mode. figure 20. power-down exit waveform exiting from power-down by reset redefines all the sfrs, exiting from power-down by external interrupt does no affect the sfrs. exiting from power-down by either reset or external interrupt does not affect the internal ram content. note: if idle mode is activated with power-down mode (idl and pd bits set), the exit sequence is unchanged, when execution is vectored to interrupt, pd and idl bits are cleared and idle mode is not entered. table 21 shows the state of ports during idle and power-down modes. note: 1. port 0 can force a 0 level. a ?one? will leave port floating. int1 int0 xtala power-down phase oscillator restart phase active phase active phase or xtalb table 21. state of ports (1) mode program memory port1 port3 idle internal port data port data power-down internal port data port data 36 at8xc5103 4134c?8051?09/04 programmable counter array (pca) the pca provides more timing capabilities wit h less cpu interventi on than t he standard timer/counters. its advant ages include reduced software overhead and improved accu- racy. the pca consists of a dedicated timer/ counter which serves as the time base for an array of five compare/capture modules. its clock input can be programmed to count any one of the following signals: ? oscillator frequency 12 ( 6 in x2 mode) ? oscillator frequency 4 ( 2 in x2 mode) ? timer 0 overflow ? external input on eci (p1.2) each compare/capture modules can be programmed in any one of the following modes: ? rising and/or fallin g edge capture, ? software timer ? high-speed output ? pulse width modulator module 4 can also be programmed as a watchdog timer. when the compare/capture modules are programmed in the capture mode, software timer, or high speed output mode, an interrupt can be generated when the module exe- cutes its function. all five modules and the pca timer overflow share one interrupt vector. the pca timer/counter and compare/capture modules share port 1 for external i/o. these pins are listed below. if the port is not used for the pca, it can still be used for standard i/o. the pca timer is a common time base for all five modules (see figure 21). the timer count source is determined from the c ps1 and cps0 bits in the cmod sfr (see table 21) and can be programmed to run at: ? 1/12 the oscillator freque ncy (or 1/6 in x2 mode) ? 1/4 the oscillator frequen cy (or 1/2 in x2 mode) ? the timer 0 overflow ? the input on the eci pin (p1.2) pca component external i/o pin 16-bit counter p1.2/eci 16-bit module 0 p1.3/cex0 16-bit module 1 p1.4/cex1 16-bit module 2 p1.5/cex2 16-bit module 3 p1.6/cex3 16-bit module 4 p1.7/cex4 37 at8xc5103 4134c?8051?09/04 pca timer figure 21. pca timer/counter table 22. cmod: pca counter mode register cmod address 0d9h cidl wdte - - - cps1 cps0 ecf reset value 0 0 x x x 0 0 0 symbol function cidl counter idle control: cidl = 0 programs the pca counter to continue functioning during idle mode. cidl = 1 programs it to be gated off during idle. wdte watchdog timer enable: wdte = 0 disables watchdog timer function on pca module 4. wdte = 1 enables it. - not implemented, reserved for future use. (1) 1. user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new fea- tures. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. cps1 pca count pulse select bit 1. cps0 pca count pulse select bit 0. cps1 cps0 selected pca input. (2) 2. f osc = oscillator frequency 0 0 internal clock f osc /12 (or f osc /6 in x2 mode). 0 1 internal clock f osc /4 (or f osc /2 in x2 mode). 1 0 timer 0 overflow 1 1 external clock at eci/p1.2 pin (max rate = f osc / 8) ecf pca enable counter overflow interrupt: ecf = 1 enables cf bi t in ccon to generate an interrupt. ecf = 0 disables that function of cf. cidl cps1 cps0 ecf it ch cl 16-bit up/down counter to pca modules fosc/12 fosc/4 t0 ovf p1.2 idle cmod 0xd9 wdte cf cr ccon 0xd8 ccf4 ccf3 ccf2 ccf1 ccf0 overflow 38 at8xc5103 4134c?8051?09/04 the cmod sfr includes three additional bits asso ciated with the pca (see figure 21 and table 21). ? the cidl bit which allows the pca to stop during idle mode. ? the wdte bit which enables or disabl es the watchdog function on module 4. ? the ecf bit which when set causes an inte rrupt and the pca overflow flag cf (in the ccon sfr) to be set when the pca timer overflows. the ccon sfr contains the run control bit for the pca and the flags for the pca timer (cf) and each module (refer to table 23). ? bit cr (ccon.6) must be set by software to run the pca. the pca is shut off by clearing this bit. ? bit cf: the cf bit (ccon.7) is set when the pca counter overflows and an interrupt will be generated if the ecf bit in the cmod register is set. the cf bit can only be cleared by software. ? bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. these flags also can only be cleared by software. ? table 23. ccon: pca counter control register the watchdog timer function is impl emented in module 4 (see figure 24). the pca interrupt system is shown in figure 22. ccon address 0d8h cf cr - ccf4 ccf3 ccf2 ccf1 ccf0 reset value00x00000 symbol function cf pca counter overflow flag. set by hardwar e when the counter rolls over. cf flags an interrupt if bit ecf in cmod is set. cf may be set by either hardware or software but can only be cleared by software. cr pca counter run control bit. set by software to turn the pca counter on. must be cleared by software to turn the pca counter off. - not implemented, reserved for future use. (1) 1. user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new features. in t hat case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. ccf4 pca module 4 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf3 pca module 3 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf2 pca module 2 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf1 pca module 1 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf0 pca module 0 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. 39 at8xc5103 4134c?8051?09/04 figure 22. pca interrupt system pca modules: each one of the five compare/capture modules has six possible func- tions. it can perform: ? 16-bit capture, positive-edge triggered ? 16-bit capture, negative-edge triggered ? 16-bit capture, both positive and negative-edge triggered ? 16-bit software timer ? 16-bit high speed output ? 8-bit pulse width modulator in addition, module 4 can be used as a watchdog timer. each module in the pca has a special functi on register associated with it. these regis- ters are: ccapm0 for module 0, ccapm1 for module 1, etc. (see table 24). the registers contain the bits that control the mode that each module will operate in. ? the eccf bit (ccapmn.0 where n = 0, 1, 2, 3, or 4 depending on the module) enables the ccf flag in the ccon sfr to generate an interrupt when a match or compare occurs in the associated module. ? pwm (ccapmn.1) enables the pulse width modulation mode. ? the tog bit (ccapmn.2) when set caus es the cex output associated with the module to toggle when there is a match between the pca counter and the module's capture/compare register. ? the match bit mat (ccapmn.3) when set will cause the ccfn bit in the ccon register to be set when there is a match between the pca counter and the module's capture/compare register. ? the next two bits capn (ccapmn.4) a nd capp (ccapmn.5) determine the edge that a capture input will be active on. the capn bit enables the negat ive edge, and the capp bit enables the positive edge. if both bits are set both edges will be enabled and a capture will occur for either transition. ? the last bit in the register ecom (ccapmn.6) when set enables the comparator function. cf cr ccon 0xd8 ccf4 ccf3 ccf2 ccf1 ccf0 module 4 module 3 module 2 module 1 module 0 ecf pca timer/counter eccfn ccapmn.0 cmod.0 ie.6 ie.7 to interrupt priority decoder ec ea 40 at8xc5103 4134c?8051?09/04 table 24 shows the ccapmn settings for the various pca functions. table 24. ccapmn: pca modules compare/capture control registers table 25. pca module modes (ccapmn registers) ccapmn address n = 0 - 4 ccapm0 (0dah) ccapm1 (0dbh) ccapm2 (0dch) ccapm3 (0ddh) ccapm4 (0deh) - ecomn cappn capnn matn togn pwmm eccfn reset valuex0000000 symbol function - not implemented, reserved for future use. (1) 1. user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new features. in t hat case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. ecomn enable comparator. ecomn = 1 enables the comparator function. cappn capture positive, cappn = 1 enables positive edge capture. capnn capture negative, capnn = 1 enables negative edge capture. matn match. when matn = 1, a match of the pca counter with this module's compare/capture register causes the ccfn bit in ccon to be set, flagging an interrupt. togn toggle. when togn = 1, a match of the pca counter with this module's compare/capture register causes the cexn pin to toggle. pwmn pulse width modulation mode. pwmn = 1 enables the cexn pin to be used as a pulse width modulated output. eccfn enable ccf interrupt. enables compare/capt ure flag ccfn in the ccon register to generate an interrupt. ecomn cappn capnn matn togn pwmm eccfn module function 0000000no operation x10000x 16-bit capture by a positive-edge trigger on cexn x01000x 16-bit capture by a negative trigger on cexn x11000x 16-bit capture by a transition on cexn 100100x 16-bit software timer/compare mode. 100110x16-bit high s peed output 10000108-bit pwm 1001x0xwatc hdog timer (module 4 only) 41 at8xc5103 4134c?8051?09/04 there are two additional registers associated with each of the pca modules. they are ccapnh and ccapnl and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. when a module is used in the pwm mode these registers are used to control the duty cycle of the output (see table 26 & table 27) table 26. ccapnh: pca modules captur e/compare registers high table 27. ccapnl: pca modules capture/compare registers low table 28. ch: pca counter high table 29. cl: pca counter low ccapnh address n = 0 - 4 ccap0h (0fah) ccap1h (0fbh) ccap2h (0fch) ccap3h (0fdh) ccap4h (0feh) 76543210 reset value 00000000 ccapnl address n = 0 - 4 ccap0l (0eah) ccap1l (0ebh) ccap2l (0ech) ccap3l (0edh) ccap4l (0eeh) 76543210 reset value00000000 ch address 0f9h 76543210 reset value00000000 cl address 0e9h 76543210 reset value00000000 42 at8xc5103 4134c?8051?09/04 pca capture mode to use one of the pca modules in the c apture mode either one or both of the ccapm bits capn and capp for that module must be set. the external cex input for the mod- ule (on port 1) is sampled for a transiti on. when a valid transition occurs the pca hardware loads the value of the pca counter registers (ch and cl) into the module's capture registers (ccapnl and ccapnh). if the ccfn bit for the module in the ccon sfr and the eccfn bit in the ccapmn sfr are set then an interrupt will be generated (see figure 23). figure 23. pca capture mode cf cr ccon 0xd8 ch cl ccapnh ccapnl ccf4 ccf3 ccf2 ccf1 ccf0 pca it pca counter/timer ecomn ccapmn, n = 0 to 4 0xda to 0xde capnn matn togn pwmn eccfn cappn cex.n capture 43 at8xc5103 4134c?8051?09/04 16-bit software timer/ compare mode the pca modules can be used as software timers by setting both the ecom and mat bits in the modules ccapmn register. the pca timer will be compared to the module's capture registers and when a match occurs an interr upt will occur if the ccfn (ccon sfr) and the eccfn (ccapmn sfr) bits for the module are both set (see figure 24). figure 24. pca compare mode and pca watchdog timer note: 1. only for module 4 before enabling ecom bit, ccapnl and ccapnh should be set with a non zero value, other/wise an unwanted matc h could happen. writing to ccapnh will set the ecom bit. once ecom set, writing ccapnl will clear ecom so that an unwanted match doesn?t occur while modifying the compare value. writing to ccapnh will set ecom. for this reason, user software should write ccapnl first, and then ccapnh. of course, the ecom bit can still be controlled by accessing to ccapmn register. ch cl ccapnh ccapnl ecomn ccapmn, n = 0 to 4 0xda to 0xde capnn matn togn pwmn eccfn cappn 16 bit comparator match ccon 0xd8 pca it enable pca counter/timer reset (1) cidl cps1 cps0 ecf cmod 0xd9 wdte reset write to ccapnl write to ccapnh cf ccf2 ccf1 ccf0 cr ccf3 ccf4 10 44 at8xc5103 4134c?8051?09/04 high speed output mode in this mode the cex output (on port 1) associated with the pca module will toggle each time a match occurs between the pca counter and the module's capture registers. to activate this mode the tog, mat, and ecom bits in the module's ccapmn sfr must be set (see figure 25). a prior write must be done to ccapnl and ccapnh before writing the ecomn bit. figure 25. pca high speed output mode before enabling ecom bit, ccapnl and ccapnh should be set with a non zero value, other/wise an unwanted match could happen. once ecom set, writing ccapnl will clear ecom so that an unwanted match doesn?t occur while modifying the compare value. writing to ccapnh will set ecom. for this reason, user software should write ccapnl first, and then ccapnh. of course, the ecom bit can still be controlled by accessing to ccapmn register. pulse width modulator mode all of the pca modules can be used as pw m outputs. figure 26 shows the pwm func- tion. the frequency of the output depends on the source for the pca timer. all of the modules will have the same frequency of out put because they all share the pca timer. the duty cycle of each module is independently variable using the module's capture register ccapln. when the value of the pca cl sfr is less than the value in the mod- ule's ccapln sfr the output will be low, w hen it is equal to or greater than the output will be high. when cl overflows from ff to 00, ccapln is reloaded with the value in ccaphn. this allows updating the pwm without glitches. the pwm and ecom bits in the module's ccapmn register must be set to enable the pwm mode. ch cl ccapnh ccapnl ecomn ccapmn, n = 0 to 4 0xda to 0xde capnn matn togn pwmn eccfn cappn 16-bit comparator match cf cr ccon 0xd8 ccf4 ccf3 ccf2 ccf1 ccf0 pca it enable cexn pca counter/timer write to ccapnh reset write to ccapnl 1 0 45 at8xc5103 4134c?8051?09/04 figure 26. pca pwm mode pca watchdog timer an on-board watchdog timer is available with the pca to improve the reliability of the system without increasing chip count. watchdog timers are useful for systems that are susceptible to noise, power glitches, or el ectrostatic discharge. module 4 is the only pca module that can be progr ammed as a watchdog. howeve r, this module can still be used for other modes if the watchdog is no t needed. figure 24 shows a diagram of how the watchdog works. the user pre-loads a 16-bit value in the compare registers. just like the other compare modes, this 16-bit value is compared to the pca timer value. if a match is allowed to occur, an internal re set will be generated. this will not cause the rst pin to be driven high. in order to hold off the reset, the user has three options: 1. periodically change the compare valu e so it will never match the pca timer. 2. periodically change the pca timer va lue so it will never match the compare values. 3. disable the watchdog by clearing the wd te bit before a match occurs and then re-enable it. the first two options are more reliable bec ause the watchdog timer is never disabled as in option #3. if the program counter ever goes astray, a match will eventually occur and cause an internal reset. the second option is also not recommended if other pca mod- ules are being used. remember, the pca ti mer is the time base for all modules; changing the time base for other modules woul d not be a good idea. thus, in most appli- cations the first soluti on is the best option. this watchdog timer won?t generate a reset out on the reset pin. cl ccapnh ccapnl ecomn ccapmn, n = 0 to 4 0xda to 0xde capnn matn togn pwmn eccfn cappn 8-bit comparator cexn ?0? ?1? < enable pca counter/timer overflow 46 at8xc5103 4134c?8051?09/04 interrupt system the at8xc5103 has a total of 5 interrupt vectors: one external interrupt int0 , two timer interrupts (timers 0, 1), pca and spi. these interrupts are shown in figure 27.. figure 27. interrupt control system each of the interrupt sources can be individually enabled or disabled by setting or clear- ing a bit in the interrupt enable register (s ee table 31). this register also contains a global disable bit, which must be cleared to disable all interrupts at once. each interrupt source can also be individually programmed to one of four priority levels by setting or clearing a bit in the interrupt pr iority register (see table 33) and in the inter- rupt priority high register (see table 35). table 30 shows the bit values and priority levels associated with each combination. ie1 0 3 high priorit y interrupt interrupt polling sequenc e low priority interrupt global disable individual enable nc nc tf0 int0 int1 tf1 iph, ip ie0 0 3 0 3 0 3 0 3 0 3 nc spi 0 3 nc 0 3 0 3 cf ccfx pca nc 47 at8xc5103 4134c?8051?09/04 table 30. priority level bit values a low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. a high-priority interrupt can?t be interrupted by any other interrupt source. if two interrupt requests of different prio rity levels are rece ived simultaneously, the request of higher priority level is serviced. if interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. thus within each priority level there is a second priority structure determined by the polling sequence. . iph.x ipl.x interrupt level priority 0 0 0 (lowest) 011 102 1 1 3 (highest) interrupt name interrupt address vector priority number external interrupt (int0 ) 0003h 1 timer0 (tf0) 000bh 2 external interrupt (int1 ) 0013h 3 timer1 (tf1) 001bh 4 pca (cf or ccfn) 0033h 5 spi 004bh 6 48 at8xc5103 4134c?8051?09/04 table 31. ie0 register ie0 (s:a8h) interrupt enable register reset value = 00xx 0000b bit addressable 76543210 ea ec - - et1 ex1 et0 ex0 bit number bit mnemonic description 7ea enable all interrupt bit clear to disable all interrupts. set to enable all interrupts. if ea=1, each interrupt source is indi vidually enabled or disabled by setting or clearing its interrupt enable bit. 6ec pca interrupt enable clear to disable the pca interrupt. set to enable the pca interrupt. 5- reserved the value read from this bit is i ndeterminate. do not set this bit. 4- reserved the value read from this bit is i ndeterminate. do not set this bit. 3et1 timer 1 overflow interrupt enable bit clear to disable timer 1 overflow interrupt. set to enable timer 1 overflow interrupt. 2 ex1 external interrupt 1 enable bit clear to disable external interrupt 0. set to enable external interrupt 0. 1et0 timer 0 overflow interrupt enable bit clear to disable timer 0 overflow interrupt. set to enable timer 0 overflow interrupt. 0 ex0 external interrupt 0 enable bit clear to disable external interrupt 0. set to enable external interrupt 0. 49 at8xc5103 4134c?8051?09/04 table 32. ie1 register ie1 (s:b1h) interrupt enable register reset value = xxxx x0xxb no bit addressable 76543210 -----espi-- bit number bit mnemonic description 7- reserved the value read from this bit is indeterminate. do not set this bit. 6- reserved the value read from this bit is indeterminate. do not set this bit. 5- reserved the value read from this bit is indeterminate. do not set this bit. 4- reserved the value read from this bit is indeterminate. do not set this bit. 3- reserved the value read from this bit is indeterminate. do not set this bit. 2 espi spi interrupt enable bit clear to disable the spi interrupt. set to enable the spi interrupt. 1- reserved the value read from this bit is indeterminate. do not set this bit. 0- reserved the value read from this bit is indeterminate. do not set this bit. 50 at8xc5103 4134c?8051?09/04 table 33. ipl0 register iph0 - interrupt priority low register 0 reset value = x0xx 0000b bit addressable. 76543210 - ppcl - - pt1l px1l pt0l px0l bit number bit mnemonic description 7- reserved the value read from this bit is in determinate. do not set this bit. 6ppcl pca counter interrupt priority bit refer to ppch for priority level 5- reserved the value read from this bit is in determinate. do not set this bit. 4- reserved the value read from this bit is in determinate. do not set this bit. 3pt1l timer 1 overflow interrupt priority bit refer to pt1h for priority level. 2px1l external interrupt 1priority bit refer to px1h for priority level. 1pt0l timer 0 overflow interrupt priority bit refer to pt0h for priority level. 0px0l external interrupt 0 priority bit refer to px0h for priority level. 51 at8xc5103 4134c?8051?09/04 table 34. ipl1 register ipl1 (s:b2h) ipl1 - interrupt priori ty low register 1 reset value = xxxx x0xxb not bit addressable. 76543210 -----pspil-- bit number bit mnemonic description 7 6- reserved the value read from this bit is i ndeterminate. do not set this bit. 5- reserved the value read from this bit is i ndeterminate. do not set this bit. 4- reserved the value read from this bit is i ndeterminate. do not set this bit. 3- reserved the value read from this bit is i ndeterminate. do not set this bit. 2 pspil spi interrupt priority level less significant bit. refer to pspih for priority level. 1- reserved the value read from this bit is i ndeterminate. do not set this bit. 0- reserved the value read from this bit is i ndeterminate. do not set this bit. 52 at8xc5103 4134c?8051?09/04 table 35. iph0 register iph0 (s:b7h) iph0 - interrupt priority high register 0 reset value = x0xx 0000b not bit addressable 76543210 - ppch - - pt1h px1h pt0h px0h bit number bit mnemonic description 7- reserved the value read from this bit is i ndeterminate. do not set this bit. 6 ppch pca counter interrupt priority level most significant bit ppch ppcl priority level 00lowest 01 10 1 1 highest priority 5- reserved the value read from this bit is i ndeterminate. do not set this bit. 4- reserved the value read from this bit is i ndeterminate. do not set this bit. 3pt1h timer 1 overflow interrupt priority high bit pt1h pt1l priority level 00lowest 01 10 1 1 highest 2 px1h external interrupt 1priority high bit px1h px1l priority level 00lowest 01 10 1 1 highest 1pt0h timer 0 overflow interrupt priority high bit pt0h pt0l priority level 00lowest 01 10 1 1 highest 0 px0h external interrupt 0 priority high bit px0h px0l priority level 00lowest 01 10 1 1 highest 53 at8xc5103 4134c?8051?09/04 table 36. iph1 register iph1 - interrupt priority high register 1 (b3h) reset value = xxxx x0xxb not bit addressable 76543210 -----pspih-- bit number bit mnemonic description 7 6- reserved the value read from this bit is i ndeterminate. do not set this bit. 5- reserved the value read from this bit is i ndeterminate. do not set this bit. 4- reserved the value read from this bit is i ndeterminate. do not set this bit. 3- reserved the value read from this bit is i ndeterminate. do not set this bit. 2 pspih spi interrupt priority level most significant bit pspih pspil priority level 0 0 lowest 01 10 1 1 highest 1- reserved the value read from this bit is i ndeterminate. do not set this bit. 0- reserved the value read from this bit is i ndeterminate. do not set this bit. 54 at8xc5103 4134c?8051?09/04 hardware byte: lock bit table 37. hardware byte (hsb) the lock system, when programmed, protec ts the on-chip program against software piracy. only one level of protection for the on-chip code which when programmed are provided. if lock bit program, no read operation can be done, only crc check. this security bit is accessible only with hardware programmer. 76543210 -lb------ bit number bit mnemonic description 7- reserved do not write this bi t 6lb user program eprom lock bit programmed (0) to protect memory from external read unprogrammed (1), read or write is allowed 5:0 - reserved do not write these bits 55 at8xc5103 4134c?8051?09/04 electrical characteristics absolute maximum ratings (1) power consumption measurement since the introduction of the first c51 device, every manufacturer made operating i cc measurements under reset, which made sense for the designs were the cpu was run- ning under reset. in our new devices, the cpu is no more active during reset, so the power consumption is very low but is not re ally representative of what will happen in the customer system. that?s why, while keepi ng measurements under reset, we present a new way to measure the operating i cc : using an internal test rom, the following code is executed: label: sjmp label (80 fe) ports 1 and 4 are disconnected, rst = v cc , xtal2 is not connected and xtal1 is driven by the clock. this is much more representative of the real operating i cc . ambiant temperature under bias: a = automotive................................................. -40 c to 125 c storage temperature ................................... -55 c to + 150 c voltage on v cc to v ss ..........................................-0.5v to + 6v voltage on any pin to v ss ..........................-0.5v to v cc + 0.5v *notice: s tresses at or above those listed under ?abso- lute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. 56 at8xc5103 4134c?8051?09/04 dc parameters t a = -40 c to +125 c; v ss = 0v; v cc = 2.7 to 5.5v; f = 0 to 16 mhz table 38. dc parameters symbol parameter min typ max unit test conditions v il input low voltage -0.5 0.2 v cc - 0.1 v v ih input high voltage except xtal1, rst 0.7 v cc v cc + 0.5 v v ih1 input high voltage, xtal1, rst vhy input hysteresis voltage 0.5 1.1 v v cc = 3.6v 0.8 1.8 v v cc = 5.5v v ol output low voltage, ports 1and 4 (6) 0.3 0.45 1.0 v v v v cc = 4.5v to 5.5v i ol = 100 a (4) i ol = 1.6 ma (4) i ol = 3.5 ma (4) 0.3 1.0 v v v cc = 2.7v to 5.5v i ol = 100 a (4) i ol = 1.6 ma (4) v oh output high voltage, ports 1 and 4. (6) pseudo bi-directional mode v cc - 0.3 v cc - 0.7 v cc - 1.5 v v v v cc = 4.5v to 5.5v i oh = -10 a i oh = -30 a i oh = -60 a v cc - 0.3 v v cc = 2.7v to 5.5v i oh = -10 a v oh output high voltage, ports 1 and 4. (6) push-pull mode v cc - 1 v cc - 0.5 v i oh = -1 ma i oh = -100 a tr ouput rise time (push-pull mode) 8 1000 ns cload = 10 pf tf ouput fall time (push-pull mode) 6 500 ns cload = 10 pf i li input leakage current 10 a 0.45v < vin < v cc r rst rst pulldown resistor 30 60 (5) 150 k ? at83c5103 (rom version) 50 90 (5) 200 at87c5103 (otp version) cio capacitance of i/o buffer 15 pf fc = 1 mhz t a = 25 c i pd power down current 10 (3) 100 av cc = 5.5 v 10 (3) 50 av cc = 3.6v i cc operating power supply current maximum values, x1 mode: (1) 0.8xf+0.8 1.2xf+1.5 ma ma v cc < 4.5v v cc > 4.5v 57 at8xc5103 4134c?8051?09/04 notes: 1. operating i cc is measured with all output pins disconnected; xtal1 driven with t clch , t chcl = 5 ns (see figure 32.), v il = v ss + 0.5v, v ih = v cc - 0.5v; xtal2 n.c.; rst = v cc ;. the internal rom runs the code 80 fe (label: sjmp label). i cc would be slightly higher if a crystal oscillator is used. 2. idle i cc is measured with all output pins disconnected; xtal1 driven with t clch , t chcl = 5 ns, v il = v ss + 0.5v, v ih = v cc - 0.5v; xtal2 n.c; rst = v ss (see figure 30.). 3. power down i cc is measured with all output pi ns disconnected; xtal2 nc.; rst = v ss (see figure 31.). 4. capacitance loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the v ol s of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions during bus operation. in the worst cases (capacit ive loading 100 pf), the noise pulse on the ale line may exceed 0.45v with maxi v ol peak 0.6v. a schmitt trigger use is not necessary. 5. typicals are based on a limited number of samples and are not guaranteed. the values listed are at room temperature and 5v. 6. if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. figure 28. i cc test conditio n, under reset figure 29. operating i cc test condition i cc idle power supply current maximum values, x1 mode: 0.6xf+0.8 1.0xf+1.5 ma ma v cc < 4.5v (2) v cc > 4.5v (2) v ret supply voltage during power-down mode 2 v table 38. dc parameters (continued) symbol parameter min typ max unit test conditions v cc i cc (nc) clock signal all other pins are disconnected. rst xtal2 xtal1 v ss v cc v cc i cc (nc) clock signal all other pins are disconnected . rst xtal2 xtal1 v ss v cc reset = v ss after a low pulse during at least 24 clock cycles v cc 58 at8xc5103 4134c?8051?09/04 figure 30. i cc test condition, idle mode figure 31. i cc test condition, power-down mode figure 32. clock signal waveform for i cc tests in active and idle modes ac parameters explanation of the ac symbols each timing symbol has 5 characters. the fi rst character is always a ?t? (stands for time). the other characters, depending on thei r positions, stand for the name of a sig- nal or the logical status of that signal. the fo llowing is a list of all the characters and what they stand for. example: t xhdv = time from clock rising edge to input data valid. t a = -40 c to +125 c (automotive temperature range); v ss = 0v; 3.135v < v cc < 3.465v the maximum applicable load capacitance for port 1 and 3 is 80 pf. timings will be guaranteed if these capacitances are respected. higher capacitance values can be used, but timings will then be degraded. rst xtal2 xtal1 v ss v cc i cc (nc) v cc all other pins are disconnecte d clock signal reset = v cc after a low pulse during at least 24 clock cycles v cc rst xtal2 xtal1 v ss v cc i cc v cc reset = v cc after a low pulse during at least 24 clock cycles v cc all other pins are disconnected . v cc -0.5v 0.45v 0.7v cc 0.2v cc -0.1 t clch t chcl t clch = t chcl = 5ns 59 at8xc5103 4134c?8051?09/04 ac testing input/output waveforms figure 33. ac testing input/ output waveforms ac inputs during testing are driven at v cc - 0.5 for a logic ?1? and 0.45v for a logic ?0?. timing measurement are made at v ih min for a logic ?1? and v il max for a logic ?0?. float waveforms figure 34. float waveforms for timing purposes as port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded v oh /v ol level occurs. i ol /i oh 20 ma. clock waveforms valid in normal clock mode. in x2 mode xtal2 signal must be changed to xtal2 divided by 2. figure 35. clock waveforms this diagram indicates when signals are clocked internally. the time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. this propagation delay is dependent on variables such as temperatur e and pin loading. pr opagation also varies from output to output and component. typically though (t a =25 c fully loaded) rd and wr propagation delays are approximately 50 ns. the other signals are typically 85 ns. propagation delays are incorporated in the ac specifications. 0.45 v vcc-0.5v 0.2vcc+0.9 0.2vcc-0.1 input/output vol+0.1 v voh-0.1 v float vload vload+0.1v vload-0.1v clock xtal2 internal state4 state5 state6 state1 state2 state3 state4 state5 serial port shift clock port operation txd (mode 0) rxd sampled rxd sampled p1, p3, p4 pins sampled p1, p3, p4 pins mov dest port (p1, p3, p4) (includes int0, int1, to, t1) old data new data p1p2 p1p2 p1p2 p1p2 p1p2 p1p2 p1p2 p1p2 60 at8xc5103 4134c?8051?09/04 ordering information part number code memory size (bytes) supply voltage temperature range max frequency packing package at87c5103-ibsil 12k otp 3.0 - 5.5v industrial 16 mhz stick ssop16 at87c5103-ibril 12k otp 3.0 - 5.5v industrial 16 mhz reel ssop16 at87c5103-icsil 12k otp 3.0 - 5.5v industrial 16 mhz stick ssop24 at87c5103-icril 12k otp 3.0 - 5.5v industrial 16 mhz reel ssop24 at83c5103xxx-ibsil 12k rom 3.0 - 5.5v industrial 16 mhz stick ssop16 at83c5103xxx-ibril 12k rom 3.0 - 5.5v industrial 16 mhz reel ssop16 at83c5103xxx-icsil 12k rom 3.0 - 5.5v industrial 16 mhz stick ssop24 at83c5103xxx-icril 12k rom 3.0 - 5.5v industrial 16 mhz reel ssop24 at87c5103-ibsal 12k otp 3.0 - 5.5v automotive 16 mhz stick ssop16 at87c5103-ibral 12k otp 3.0 - 5.5v automotive 16 mhz reel ssop16 at87c5103-icsal 12k otp 3.0 - 5.5v automotive 16 mhz stick ssop24 at87c5103-icral 12k otp 3.0 - 5.5v automotive 16 mhz reel ssop24 at83c5103xxx-ibsal 12k rom 3.0 - 5.5v automotive 16 mhz stick ssop16 at83c5103xxx-ibral 12k rom 3.0 - 5.5v automotive 16 mhz reel ssop16 at83c5103xxx-icsal 12k rom 3.0 - 5.5v automotive 16 mhz stick ssop24 at83c5103xxx-icral 12k rom 3.0 - 5.5v automotive 16 mhz reel ssop24 61 at8xc5103 4134c?8051?09/04 package drawings ssop 16 leads 62 at8xc5103 4134c?8051?09/04 ssop 24 leads 63 at8xc5103 4134c?8051?09/04 datasheet revision history for at8c5103 changes from 4134a- 05/02 to 4134b-04/03 1. changed the reset pulldown resistor for rom version (see ac/dc parameters). changes from 4134b- 04/03 to 4134c-09/04 1. changed the section ?hardware byte: lock bit?, page 54. printed on recycled paper. ? atmel corporation 2004. all rights reserved. atmel?, logo and combinations thereof are regi stered trademarks, and everywhere you are(sm) are the trademarks of atmel corporation or its subsidiari es. other terms and product names may be trademarks of others. disclaimer: atmel corporation makes no warranty for the use of its products, other than those ex pressly contained in the compan y?s standard warranty which is detailed in atmel?s terms and conditions locat ed on the company?s web site. the company assumes no responsibi lity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained her ein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel produc ts, expressly or by implicati on. atmel?s products are not aut horized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 487-2600 europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel (33) 2-40-18-18-18 fax (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel (33) 4-42-53-60-00 fax (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel (44) 1355-803-000 fax (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel (49) 71-31-67-0 fax (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf data- com avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-76-58-30-00 fax (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com 4134c?8051?09/04 0m |
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